Integrated circuit designers use a variety of components to implement desired circuit functionality. These components may include bipolar and field-effect transistors, junction diodes, capacitors, and resistors.
Capacitors are used in a wide variety of applications which require charge storage elements. An integrated circuit capacitor and integrated circuit resistor form a characteristic time constant useful as a delay element or for signal frequency filtering applications. Capacitors are particularly useful for power supply decoupling of digital complementary metal-oxide-semiconductor (CMOS) circuits which draw large transient current spikes during switching. A large capacitance connected between the power supply and ground can supply much of the charge drawn during these transient switching events, thereby smoothing the power supply voltage. Charge pump circuits are another application in which capacitors may be used. In charge pump circuits, MOS switches or pn junction diodes are used to control conduction of charge; the capacitors may be switched to convert an input power supply voltage to an output power supply of different voltage or polarity.
Integrated circuit capacitors can be implemented in a variety of different ways. A parallel plate capacitor constructed from two conductive plates separated by a dielectric layer. The conductive plates may each be composed of a metal, one conductive plate could be conductively doped polysilicon and the other conductive plate could be metal, or both conductive plates may be composed of conductively doped polysilicon. Such parallel plate capacitors may require additional process steps in forming a thin dielectric between the conductive plates, or in forming the conductive plates. In a metal-oxide-semiconductor (MOS) process, a MOS field-effect transistor (FET) having drain, gate, source, and body regions may also be used as a capacitor (MOS capacitor). Use of a MOS capacitor is advantageous since no process complexity is added to implement the capacitor; only existing process steps are used.
In FIG. 1, a schematic cross-sectional view of one embodiment of an n-channel MOS (NMOS) FET is illustrated. The NMOS FET has a conductively doped polysilicon gate region 100 formed on a thin dielectric region 110 which is formed on a lightly p-type doped substrate 120. Source region 130 and drain region 140 comprise heavily n-type doped diffusion regions.
In FIG. 1, the NMOS FET device is capable of being used as a capacitor. Such an NMOS capacitor 145 has a top plate comprising the conductively doped polysilicon gate 100. The bottom plate comprises the lightly doped semiconductor substrate 120 (body region of the FET). The top plate and bottom plate of the NMOS capacitor 145 are separated by the thin dielectric region 110.
The NMOS capacitor 145 bottom plate comprises a lightly doped semiconductor substrate 120 which has distinct regions of operation: accumulation, depletion, and inversion. These regions of operation are defined by the voltage applied to the NMOS capacitor 145. The NMOS capacitor 145 has a capacitance value which depends on the applied voltage, as described in Ben G. Streetman, Solid State Electronic Devices. 3rd ed., Prentice-Hall (1990).
FIG. 2 illustrates the NMOS capacitance 150 as a function of a voltage 160 which is applied to the gate 100 of the NMOS capacitor 145 with the bottom plate, substrate 120, held at ground voltage potential at 0 V. In particular, as a positive dc voltage is applied to gate 100, the NMOS capacitance between the gate 100 and the substrate 120 decreases until a characteristic threshold voltage (Vt) 170 is reached, beyond which capacitance increases. Because of its reduced capacitance for positive voltages less than Vt applied to the gate 100, the NMOS capacitor 145 is most useful for such voltages which exceed Vt. Thus, the Vt of the NMOS capacitor 145 limits its useful voltage range.
Similarly, FIG. 3 illustrates a schematic cross-sectional view of a p-channel MOS (PMOS) FET device. The PMOS FET has a conductively doped polysilicon gate region 180 formed on a thin dielectric region 190 which is formed on a lightly n-type doped substrate 200. Source region 210 and drain region 220 comprise heavily p-type doped diffusion regions. The PMOS FET device is capable of being used as a capacitor. The top and bottom plates of PMOS capacitor 225 are separated by the thin dielectric region 190.
FIG. 4 illustrates the PMOS capacitance 230 as a function of a voltage 240 which is applied to the gate 180 of the PMOS capacitor 225 with the bottom plate, substrate 200, held at ground voltage potential. In particular, as a negative dc voltage is applied to gate 180, the PMOS capacitance between the gate 180 and the substrate 200 decreases until a characteristic threshold voltage (Vt) 250 is reached, beyond which capacitance increases. Because of its reduced capacitance for voltages between Vt and 0 V applied to the gate 180, the PMOS capacitor is most useful for voltages more negative than Vt. Thus, the magnitude of the threshold voltage Vt of the PMOS capacitor limits its useful voltage range.
As semiconductor technology progresses and device dimensions are scaled downward, power supply voltages are typically reduced to keep electric fields within the FET devices within an acceptable value. Power supplies are also lowered to reduce power consumption of integrated circuit die used in portable electronic devices. As the power supply voltages are reduced, the effect of the magnitude of Vt on the useful voltage range of the MOS capacitor becomes increasingly important.